The present invention generally relates to circuit area analysis on integrated circuit layouts and in particular, to a method for eliminating false failures saved by redundant paths during circuit area analysis on an integrated circuit layout.
Circuit area analysis predicts failures of an integrated circuit that result from probabilistic defects. One common problem with conventional circuit area analysis techniques is their general inability to eliminate false failures saved by redundant paths during the circuit area analysis. This deficiency may result in overly conservative design and unnecessary testing for false failures, both of which add unwarranted cost to the manufacture of the integrated circuit.
Accordingly, an object of the present invention is a method for eliminating false failures saved by redundant paths during circuit area analysis on an integrated circuit layout.
This and additional objects are accomplished by the various aspects of the present invention, wherein briefly stated, one aspect is a method for eliminating false failures saved by redundant paths during critical area analysis of an integrated circuit layout, comprising: identifying vertices significantly encroached by one or more simulated defects; and eliminating false failures resulting from the one or more simulated defects if all nets including at least one of the identified vertices have at least one redundant path that does not include any of the identified vertices.
Another aspect is a method for eliminating false failures saved by redundant paths during critical area analysis of an integrated circuit layout, comprising: identifying vertices significantly encroached by one or more simulated defects; retrieving predefined sets of vertices associated with individual of nets including at least one of the identified vertices; and indicating a failure resulting from the one or more simulated defects for each instance where all elements of at least one of the predefined sets of vertices are one of the identified vertices.
Additional objects, features and advantages of the various aspects of the invention will become apparent from the following description of its preferred embodiments, which description should be taken in conjunction with the accompanying drawings.